This chapter takes you through a rather more complicated design than you encountered earlier. The circuit to be constructed is shown in Figures 4.1and 4.2. It is intended to allow the serial port of a personal computer to be used to send and receive data in parallel form.

 

You should familiarise yourself with the essential features of the serial port and the general characteristics of serial data transfer. A good place to look is www.taltech.com/introserial.htm

 

You will also need to know something about how to program a serial port. Here you could try

http://www2.crosswinds.net/oklahoma-city/~jbgizmo/page2.html

 

The circuit comprises two essential blocks. The first is based on the SP232 device and is concerned with voltage level conversion. The purpose of this device is to change the electrical characteristics of the signals. The electrical specification of the serial port is contained in the EIA (Electronics Industries Association) RS232C Standard. A logic 0 (space) is required to be between +3V and + 25V. A logic 1 (mark) is required to be between -3V and -25V. The rest of the circuit uses TTL logic levels and the SP232 makes the necessary conversions. Thus the RS232C data received by the chip on pin 13 is output at pin 12 with its levels set to TTL values i.e. a logic zero is between 0V and 0.4V and a logic high is between 3.5V and 5V. In the reverse process data sent to the PC is converted into RS232C levels as it passes from pin 10 to pin 14.

 

The second block is the HD-6402. This chip receives data in serial form on pin 20, clocks it into a internal register, strips off the start, stop and parity bits and outputs the data on pins 6 - 13 in parallel form.

 

Parallel data on pins 27 - 33 can be converted into serial form, start stop and parity bits added and the serial data transmitted from pin 25 to the PC.

 

Associated with the HD-6402 is the timer chip NE555. This is used as a clock generator. The data transmission rate for the HD-6402 is equal to the clock frequency divided by 16. The standard transmission rates for serial connections include 300, 1200, 2400, 4800, 9600 Baud. We are going to use 1200 Baud so the required clock frequency is 19.2 kHz.

 

In the first part of this study we will restrict our interest to the use of the circuit for outputting parallel data. In other words we will program a PC to send data from its serial port and the circuit will receive the data and make the conversion to parallel TTL voltage signals

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Figure 4.2                      

The clock schematic page

A hierarchical design is a design structure in which schematics are interconnected vertically with hierarchical blocks. At least one schematic page, the root or parent, contains symbols representing other schematics.

 

If time permits we will also look at the inverse task, namely that of reading parallel inputs and sending them to the PC in serial form.

 

 

The schematics drawn here introduce some features which we did not mention in Chapter 1. The first is the use of a hierarchical block to hide away the details of the timer circuitry. This makes the schematic page a lot less cluttered than if the timer circuit were included.

 

A hierarchical design is a design structure in which schematics are interconnected vertically with hierarchical blocks. At least one schematic page, the root or parent, contains symbols representing other schematics.

 

A hierarchical block is a symbol that refers to a child schematic in a design. The connection points on a hierarchical block are called hierarchical pins and hierarchical ports. You place a hierarchical block using the Hierarchical Block command on the Place menu.

To attach a schematic to a hierarchical block

 

1                 Open the schematic page editor on the parent page.

2                 From the Place menu, choose the Hierarchical Block          command .

3                 Assign a name to the hierarchical block. Do not click OK.

4                 Choose the Attach Schematic button. The Attach   Schematic dialog box displays.

5                 In the Schematic text box, enter the name of the child         schematic, usually the same as that of the Hierarchical                   Block.

6                                   If the child schematic is not in the current design, specify the path and library where the schematic is located. Otherwise leave this field blank.

7                                   Choose the OK button twice. The parent schematic page displays.

8                                   Draw the hierarchical block.

9                                   With the block selected click View, Descend Hierarchy. Enter a name for the schematic page which will contain the circuit diagram and click OK.

 

Your design will now have a new schematic with the same name as that of the block on the parent sheet. In the schematic there will be a new schematic page in which you will enter the circuit diagram of the block.

 

If the block schematic page is open you can climb up to the root schematic page using View, Ascend Hierarchy. You can descend again using View, Descend Hierarchy.

 

The second feature is the use of a bus to join the input pins of the 6402 to the header. A bus is a compact way of showing many connections. To place a bus select Bus from the Part menu and draw it as you would a wire. If you hold down the shift key as you draw you can draw angles other  than 90^o.

 

A bus needs to be properly drawn and labelled however if it is to be interpreted correctly.

Entries from individual pins to the bus are made by means of Bus entries \ or /. These are available from the Place menu. (Left click on the entry to rotate it.) Do not use wires as entries. Connections from a Bus entry to a pin cannot be made directly, you must insert a length of wire first. The wire must be labelled at both ends with a Net Alias and the bus itself must carry a Net Alias of the form R[1..7]. Follow the procedure shown in the diagram and all will be well.

 

Draw the schematics shown in Figures 4.1 and 4.2. Use the Part Search facility in the Place Part Dialogue box to locate the libraries which contain the required parts.

 

When you have finished the drawings run Design Rules Check. Do not attempt to proceed until DRC returns no errors.

 

 

To prepare the circuit for PCB production it is necessary to find suitable footprints for each part.

 

Gather together all of the components first so that you know what you are looking for.

 

You can examine the Layout Footprint libraries to find the required footprints as follows.

 

Start Layout and Click File, New and dismiss the Load Template File box by pressing Cancel. The design environment appears. Then select Tool, Library Manager. At the left a panel appears containing a list of all of the footprint libraries. Select a library and the contents is displayed in the lower panel. Click on an entry and the footprint is shown on the main screen. If you can't find a suitable footprint you can create your own.

 

To create a footprint

 

1                 In the library manager, choose the Create New Footprint    button.

2                 Enter the name for the footprint.

3                 If the footprint is to be metric, select the Metric option.

4                 Choose the OK button to dismiss the dialog box. The          footprint origin, one pin, and default text objects display in               the footprint editor.

5                 In the System Grids dialog box, establish the placement       grid. This determines the spacing of the padstacks.

 

To add a pin to the footprint

 

1                 In the footprint editor, choose the Pin command from the    Tool menu.

2                 Select the first pin (one pin is placed when you create the   footprint using the Create New Footprint command in the           Library Manager). From the pop-up menu, choose the                    Insert command.

3                 Position the pin in the desired location. Use the X and Y     coordinates displayed in the status bar as guides.

4                 Click the left mouse button to place the pin. Placing this      pin establishes the pin-to-pin spacing on the current side of              the footprint.

5                 For each additional pin, select the Insert command.

 

To place additional rows of pins

 

1                 Select a pin and choose the Insert command.

2                 Position and place the pin.

3                 Again, choose the Insert command for each additional pin   you want to place in the row. Placing the second pin     establishes the pin-to-pin spacing for the row.

4                 Repeat these steps until all the pins are in place.

 

To assign one padstack to all the pins of a footprint

 

1                 Choose the spreadsheets toolbar button.

2                 Select Footprints from the drop-down list.

3                 In the Footprints spreadsheet, double-click on the footprint name.

4                 Select a padstack from the Padstack Name drop-down list.

5                 Choose the OK button to accept the setting and close the    dialog box.

 

To assign a padstack to an individual pin

 

1                 In the footprint editor, choose the Pin tool from the toolbar.

2                 Press the SHIFT key and select the pin. From the pop-up   menu, choose Modify.

3                 Select a padstack for the pin from the Padstack Name drop-           down list.

4                                   Choose the OK button to close the Edit Pad dialog box.

 

It is a good idea to save any new footprints you create in a library of there own rather than saving them in existing libraries. In this way you can copy the new library to floppy disk to take away with you. To create a custom footprint library

 

1                 In the Footprints window, select a footprint to save to the    new library. The footprint displays in the footprint editor.

2                 Choose the Save As button. The Save Footprint As dialog   box displays.

3                 Choose the Create New Library button. The Create New   Library dialog box displays.

4                 Enter the name for the new library in the File name text      box, select a target directory for the library, and choose the             Save button.

5                 Choose the OK button to exit the Save Footprint As dialog box. The new library is added to the bottom of the list of         available libraries in the Libraries window.

6                 Add footprints to the library.

 

To add or copy footprints to libraries

 

1                 In the footprints window, select the footprint name. The      footprint displays in the footprint editor.

2                 Choose the Save As button. The Save As Footprint As       dialog box displays.

3                 Select a library from the drop-down list.

                   or

                   Choose the Browse button. Locate and select the desired   library.

                   or

                   Create a new library.

4                 Choose the OK button.

 

To delete footprints from libraries

 

1                 In the library manager, select a footprint in the footprints     window.

2                 Choose the Delete Footprint button. Layout asks you to      confirm your decision to remove the footprint.

3                 Choose the Yes button.

 

When you have a footprint for each component, return to Capture, edit each component and insert the footprint name in the appropriate field.

 

Then create a layout netlist following the procedure described in Chapter 3.

 

 

As this circuit is significantly more complicated than the earlier ones we will use a two layer board i.e. one with tracks on both sides. A two layer board requires that the pins of the components can make connections to the tracks on both of the layers. To achieve this a process called plating through is used in which the holes drilled to accommodate the pins are lined with conducting material. This is usually accomplished using chemical means but we will use a simple mechanical procedure specially intended for prototyping. A special kit is available in the Electronics Workshop.

 

The default settings in your chosen template for such design parameters as track width, via spacing, pin diameter etc. may be rather too fine for the manufacturing facilities available to us so you should modify all of these to make the manufacturing process easier. Some suggested parameter values, suggestions for a routing strategy and some other tips are given for your guidance.

 

Make sure that all ground and power objects on your schematic pages have the same names. If you have a GND POWER and a GND SIGNAL they will be connected to different nets even though they have the same symbol.

 

If you make any changes to the schematics you can communicate then to Layout by enabling Run ECO to Layout in the Capture Create Netlist Utility.

 

Set up routing on the top and bottom layers only from the Layers spreadsheet. Place the board outline on the Global Layer.

 

Place and lock the components. Run Place Design Check before proceeding.

 

Select a pad size of 75 mils from the padstack spreadsheet for all pads and vias.

 

Route the major nets individually. Choose the nets spreadsheet and enable routing on the GND net only. Set the width to 20 mils. Then enter Options, Grid and set the Routing Grid and the Via Grid to 35 mils. This ensures that the etched tracks are not too thin and that they are not too close together. From the View Menu select DRC Box and select the whole design. Then select Auto, Route Window.

 

You should find that the design is routed on the top and bottom layers with vias inserted automatically to connect between the layers. If you don't like any of the routes you can change them. Suppose you wanted to route a track onto a different layer. Select the layer on which the track is located by typing 1 (TOP) or 2 (BOTTOM) Select the track and right click the mouse. A set of options appears to edit the track.

 

Ripup Net removes all routes

Ripup Conn removes the selected route pin to pin.

Ripup Segment removes the selected segment of a route.

 

To replace a route, click on the ratsnest, start at a pin and draw the route to the destination pin following a suitable path. Left click to change direction, right click to change the routing properties. If you cross a route on the same layer a via will be placed and routing continued on the next layer if Design Rules Check is enabled. If you want to place a via yourself simply left click as you trace the route and type the number of the layer you wish to change to.

 

Then reopen the Net spreadsheet and enable routing on the Vcc net and select a suitable track width. Run Autoroute again and examine the result. Change anything you don't like.

 

Finally enable routing on all the remaining nets, select a suitable width and autoroute.

 

If you have placed your components well, Autoroute should complete all tracks. If any tracks are left unrouted you should either route the remaining tracks manually or re-locate one or more components. Choosing connections to parts such as headers can often help the routing process.

 

Remember that when you come to make the board drilling and inserting vias is a tedious process. Try to find component locations which will minimise the number of vias. Look at the statistics spreadsheet to keep track of the number of vias used in your design.

 

Once the routing is completed to your satisfaction produce the masks and make the board. Options are available in the Post Process spreadsheet to modify the printout.

 

 

 

 This exercise is part of your professional development course and your work will be assessed. The criteria to be used in the assessment process are as follows:

 

A pass grade (E) will be awarded for a report which details

the operation of the circuit,

the schematic pages drawn for pcb layout

the artwork for pcb production

a construction and test schedule for the circuit. This should include simple software listings in a language of your choice.

 

An A grade will be awarded if, in addition to the pass requirements, you manufacture a board which works as required. The board should be submitted for assessment and the quality of manufacture will be appraised. You should document carefully the construction strategy you adopted. You will need to demonstrate the working board.

 

Work falling between these two extremes will gain intermediate grades.